Domino Static Gates Final Design Report

Static circuit gates are the standard circuit devices used to build the major parts of digital circuits. Dynamic gates, such as domino circuits, are only used in certain sections of the circuit where speed is critical. These gates achieve higher speed compared to static gates at the cost of reduced noise margins. We propose a novel gate structure that tries to improved noise margin when compared to dynamic domino gates with a standard keeper while retaining some advantage over static gates in terms of performance and switching energy. Here we make a comparison between static, dynamic domino, dynamic domino with noise tolerant precharge and our novel domino static gates in terms of noise, switching energy and transition delay. Motivation Dynamic domino gates are able to achieve lower delays and less switching energy when compared to static gates because of their ability to source substantially more output current for the same input load capacitance. This is because, by design, the less effective PMOS gates are not connected to the inputs that drive the output low and there is only a single PMOS transistor for driving the output high. This configuration achieves further power reductions due to the reduced contention between the pull-up and the pull-down sections of a domino gate, since the pull-up and pull-down sections of the gate are not switched on simultaneously. The drawback of this design is that the output node is left floating for some time making it susceptible to noise and reduces the usability of the gate. Hence improving noise margins will allow domino gates to be more robust and increase their usable design space. Improving the noise margin will affect other important parameters like delay, power and size of the circuit. Understanding the tradeoff between performance, noise and energy is necessary to optimize the design of these gates given their particular circuit environment and demands. The a new gate topology tried in this project has characteristics of both static combinational gates and dynamic domino gates. We do some characterization of input noise of the gate in terms our three critical parameters: performance, noise and energy. The results of our new circuit topology are compared against our benchmark of static gates, domino gates with NTP and domino gates. Introduction Static gates are those in which the output is always driven with a low impedance path to either power or ground. A combinational static gate is one in which the path is exclusively driven by input signals to the gate. In order to achieve this, the path to power is the dual or complement of the path to ground. Each input will therefore drive both PMOS and NMOS transistors. Since domino gates have independent paths to power and ground, most of the inputs do not drive both PMOS and NMOS transistors. In domino gates, 1 the path to power and ground only need to be asserted to flip the state of the output from high to low and vice versa. When the path to power or ground is not asserted, the output is floating. In these states the output is dependent on its previous state. The floating output node of the dynamic domino gate makes it very vulnerable to noise and causes its noise margin to be heavily dependent on the threshold voltage whereas the noise margin of static gates is higher. Scaling results in reduced supply voltages and this increases the effect of noise as the ratio of noise to rail voltage increases. This is further compounded by the fact that threshold voltage has not scaled well and the resulting reduction in the difference between the threshold voltage and the rail voltage. Some techniques used to increase the noise margin of domino gates while retaining some of their advantage of speed and lower switching energy compared to static gates have been illustrated in Figure 1 and discussed below. 1. Keeper transistors: This circuit structure is shown in Figure 1(a). This circuit is a simple feedback circuit consisting of two inverters to maintain the output at its previous state despite the noise and charge sharing in dynamic domino circuits. This feedback circuit does not leave the output node floating and provides a pullup or pull-down path for the output at all times. This provides a path for the output node to recover from the effects of noise and thus increases the noise margin. This structure also results in contention between the pull-up structure of the dynamic gate and the pull-down structure of the feedback and vice versa causing an increase in switching energy and reduced speed. In some cases, the pull-down section of the feedback (shown within the box) is omitted as keeping the output low is not considered important. 2. Noise Tolerant Precharge (NTP) circuit: This circuit structure is shown in Figure 1(b). This circuit structure basically provides a weak pull-up structure along with the dynamic gate resulting in the implementation of f(x) + pch where f(x) is the function implemented by the pull-down structure of the dynamic gate. This circuit does not have a feedback and does not need an additional pull-down structure. This structure essentially forms a static gate with an additional pull-up path pch. Hence this circuit structure also suffers the same contention issues as in a static gate [1] [2]. 3. Domino Static Gate: This is the novel circuit topology which is shown in Figure 1(c). This circuit structure aims at reducing the contention between the pullup structure of the feedback and the pulldown structure of the dynamic gate and vice versa as seen in the gate structure using keeper transistors. This can help reduce the switching energy required and increase the speed of the gate. This gate structure can also be used to improve the noise margin and performance of the dynamic gate when used in the set/reset mode of operation and not just for clocked operation like the NTP topology discussed above. This structure will be discussed in more detail in the next section.